Context
FPGA accelerators (AMD/Xilinx Alveo U250) offer tremendous potential for accelerating diverse workloads: cryptography, AI training/inference, signal processing, and more. However, unlike NVIDIA’s CUDA ecosystem which democratized GPU access, there is no equivalent standardized abstraction layer for FPGAs.
AMD/Xilinx’s XRT (Xilinx Runtime) provides building blocks for kernel execution, but remains low-level and not easily accessible for application developers.
Objective
Design and develop a generic driver/framework that plays for FPGAs the same role CUDA plays for NVIDIA GPUs:
- Hardware abstraction for FPGA via XRT
- Standardized interface for loading and executing kernels
- Maximum genericity: support future kernels (hash, AI, DSP…)
- Facilitate kernel usage by non-FPGA-expert developers
Primary Use Case: Hashcat Integration
The first concrete goal is to integrate our SHA256 FPGA kernel with Hashcat (the industry-standard password cracking tool). Hashcat should see our FPGA as a “custom GPU” and transparently offload hashing operations.
Project Phases
Phase 1: Technology Watch (2 months)
- State of the art report
- Architecture proposal
Phase 2: Architecture Design (1 month)
- Technical architecture
- API specification
Phase 3: PoC Implementation (2 months)
- Driver core development
- Hashcat/SHA256 integration
Phase 4: Validation & Documentation (1 month)
- Benchmarks
- Final report
- Defense preparation
Required Skills
Essential
- Programming: Strong foundations in system architecture and low-level programming (C/C++)
- Parallel Computing: Knowledge of parallel programming (CUDA, OpenCL, or equivalent)
- Heterogeneous Architectures: Interest in CPU/GPU/FPGA systems
- Autonomy: Analytical skills and proactive mindset
Appreciated
- Experience with Xilinx Vitis/Vivado or HLS
- Familiarity with Linux drivers and/or embedded systems
Technical Environment
- FPGA Hardware: AMD/Xilinx Alveo U250
- Framework: Xilinx Runtime (XRT), Vitis
- Languages: C/C++, Python (tooling)
- OS: Linux (Ubuntu)
Internship Details
- Duration: 6 months
- Team Size: 1-2 engineers
- Profile: Final year engineering student with R&D/innovation mindset
- Location: WiseCorp (Tunisia) / Remote possible